With each succeeding generation, semiconductor integrated circuits increase in speed and their features proliferate. Two factors govern the speed of signal transmission in semiconductor circuits: 1) switching time (gate delay component) in the transistor portion, and 2) the time that an electrical signal is propagated in a circuit (wiring delay component). The gate delay component tends to decrease with the reduction of transistor size, while the wiring delay component tends to increase with the refinement, i.e., diminuation, in size of wiring layers and the increasing complexity of wiring circuitry. Since wiring delay is determined by the product (C×R) of wiring capacity C and wiring resistance R, the use of Cu as a material for wiring has been enthusiastically studied as a means of restricting wiring delay since it has a lower resistance than Al which has traditionally been used.
Damascene refers to a process in which interconnect metal lines are delineated by isolating dielectrics. Damascening is not performed by lithograpy and etching, but by chemical-mechanical planarization (CMP). In damascening, an interconnect pattern is first lithographically defined in the layer of dielectric, then metal is deposited to fill in the resulting trenches. Then excess metal is removed by means of chemical-mechanical polishing (planarization).
Chemical-mechanical polishing (CMP), also called chemical-mechanical planarization, refers to a method of removing layers of solid by chemical-mechanical polishing carried out for the purpose of surface planarization and definition of the metal interconnect pattern.
Dual damascene is a modified version of the damascene process which is used to form metal interconnect geometry using a CMP process instead of metal etching. In dual damascene, two interlayer dielectric patterning steps and one CMP step create a pattern which would otherwise require two patterning steps and two metal CMP steps when using a conventional damascene process.
FIGS. 1(a) through 1(d) are drawings explaining a conventional method of manufacturing a semiconductor device having dual damascene structure wiring.
In a first conventional method of manufacturing, a first silicon nitride (Si3N4) film 3, a first silicon oxide film 4, a second silicon nitride (Si3N4) film 5 and a second silicon oxide film 6 are successively formed over a layer insulation film 2 in which a first wiring layer 1 is embedded. This is shown in FIG. 1(a). The first wiring layers are formed on a substrate, not depicted in the drawings for the sake of brevity.
Next, anisotropic dry etching to open via hole 8 is performed using a first photoresist 7 as a mask. This etching is performed until the first nitride film 3 is exposed in the interior of via hole 8. The first nitride film 3 acts as a stopper film that stops the progress of etching in this etching process as shown in FIG. 1(b).
When the etching to open via hole 8 is finished, the first photoresist 7 is removed from above the second silicon oxide film 6, and a second photoresist 9 which has an open portion that corresponds to the wiring slot 10 is formed in its place, as shown in FIG. 1(c).
Next, anisotropic dry etching to open wiring slot 10 is performed using the second photoresist 9 as a mask. This etching is performed under the condition that a silicon oxide film can be removed with a significant selection ratio to the silicon nitride film. At this time, the first silicon nitride film 3 and the second nitride film 5 are both used as stopper films which stop the progress of etching. Next, etching for the purpose of removing the second silicon nitride film 5 exposed in the bottom of wiring slot 10 and the first silicon nitride film 3 exposed in the bottom of via hole 8 is performed. If this processing is done properly, via hole 8 which exposes the surface of first wiring layer 1 and wiring slot 10 which leads to via hole 8 are formed as shown in FIG. 1(d).
However, with respect to the first silicon nitride film 3, in the etching process to form wiring slot 10, the bottom portion of via hole 8 is exposed to etchant gas (hereafter that portion will be referred to as the “exposed portion”). Likewise, that exposed portion is substantially etched in the etching process to open the wiring slot 10 due to variation in the manufacturing conditions. Under these circumstances, during the etching process to open the wiring slot 10, via hole 8 goes through the first silicon nitride film 3 and the surface of the first wiring layer 1 may be exposed. Such being the case, damage to the first wiring layer 1 occurs due to continued subsequent etching as shown in FIG. 2, and the resistance value may increase as a result.
In an effort to solve these problems in this conventional dual damascene method, it has been proposed to fill the previously noted via hole 8 with a polymer such as a photoresist during the process of forming wiring slot 10, thereby protecting the first wiring layer 1. FIGS. 3(a) through 3(d) illustrate a method of forming a dual damascene structure with this previously proposed method. In FIGS. 3(a) through 3(d), the same reference numbers have been used as in the previous explanation and therefore will not be explained.
A polymer film 11 (See FIG. 3(b)) is formed so that the via hole 8 will be embedded in the silicon nitride film at the time the structure of FIG. 3(a) is formed. In the process of FIG. 3(c), the residual polymer film on the silicon oxide film is eliminated by etching back. Next, in FIG. 3(d) a second resist pattern having an open portion in the place corresponding to wiring slot 10 is formed by such techniques as photolithography and electron beam lithography. Using this as a mask, previously noted wiring slot 10 is formed by etching back. In this process, polymer film 11 restricts the damage that the first wiring layer 1 will sustain from the etching process.
When using this previously noted process, it is difficult to control the depth of polymer film 11 in the etching back process of FIG. 3(c). When this etching back process is conducted in oxygen plasma, the etching speed becomes very fast due to the etching speed planar distribution being non-uniform. Further, when etching with oxygen plasma in this way, the polymer that adheres to the walls of the reaction chamber of the dry etching device peels off due to exposure to the oxygen plasma. This detritus becomes particles which adhere to the semiconductor or device substrate, thereby causing contamination problems such as the formation of defects. While problems like these may be at least partially avoided by performing the etch back process of FIG. 3(c) in a special dry etching device, the manufacturing process for semiconductors thereby becomes highly complex and thus increases manufacturing costs.
As an alternative to the method which peels off the polymer layer using the etching back method, a method which replaces the previously noted polymer film 11 with a photosensitive resin which can be dissolved by alkali was proposed in Japanese Unexamined Patent Application 2000-188329. In this technique, after the process of applying the polymer film of FIG. 3(b), the entire wafer surface is subjected to a light of a set wavelength, and the light sensitive portion is removed by an alkali aqueous solution. However, defects tend to occur and, as before, there were problems with reliability of the process for removing the polymer layer with an alkali aqueous solution. In addition, with the polymer removal process it is necessary to use a special high precision developing device, which further increases manufacturing costs.
Besides the two previously noted methods, as in Japanese Unexamined Patent Application 10-223755, there is a method of forming a resist pattern by applying a polymer film 11 such as an organic reflection preventing film without performing an etch back process. This simplifies the process, but the polymer film adhering to the side walls of the via hole becomes a mask when etching the layer insulation film around the via hole, and a layer insulation film residue 12 which has a fence configuration around the via hole occurs. Such a layer of photoresist film residues with a fence configuration causes variations in the resistance value of the wiring layer.
As has been shown, conventional semiconductor processing forms fence structures around the via hole, and disadvantageous resistance variations in the wiring layer result. Further, conventional semiconductor processing causes contamination problems and the associated proliferation of defects.